Impact of failure mechanism on device and circuit performance

In a circuit environment, the reliability of electron devices can substantially differ from the one determined using laboratory test conditions. In this sense, in the last years, the problem of reliability evaluation has been reformulated, questioning on the correct behaviour of the circuit after the failure of the device. From this new point of view, it is essential to understand how the different failure mechanisms affect the behaviour of the MOSFET, a knowledge that cannot be gained without the perspective of the physical phenomena that take place. The introduction of materials with a large dielectric constant (high-k) as gate dielectrics rises new questions on the device reliability. The variability associated to the 45nm and beyond CMOS technology nodes has to be also considered.

REDEC’s efforts in this field are devoted to the study of the impact of the gate dielectrics failure after electrical stress on the electrical characteristics of devices and on their SPICE description, to simulate the circuit reliability. Time Dependent Dielectric Breakdown (TDDB), bias temperature instability (BTI) and Channel Hot Carrier (CHC) effects are considered on SiO2 and high-k based devices.

 

SOME RESULTS

Dielectric degradation and breakdown in devices with SiO2 dielectric

 

Characterization of the dielectric degradation and breakdown (BD) in SiO2 based devices. The gate dielectric wear-out produces a decrease of the saturation current and an increase of the threshold voltage and transconductance of the transistor. These effects are stronger in FinFET transistors. The results show that the transistor characteristics variation depends on the hardness and location in the channel of the breakdown path and on the transistor geometry.

Post-breakdown description of the electrical behavior of SiO2 based devices. The electrical stress leads to an increase of the gate leakage and also to a variation of the conduction along the channel. The variation of the conduction along the channel is described by the BSIM4 transistor model, with a new set of parameters. The post-breakdown gate current is accounted for by adding external circuitry (voltage controlled current sources or circuits with diodes and resistors). This description of the MOSFET post-breakdown performance can be easily included in a circuit simulator.

 

Effect of the dielectric degradation on circuit functionality

 

Circuit reliability simulation: inclusion of the gate SiO2 based transistors failure. The models developed for the degraded/broken down devices have been included in a circuit simulator to observe the impact of the dielectric degradation and breakdown on circuit functionality. The performance of an NMOS current mirror is strongly affected by the variation of the channel current whereas RS flip-flops are mainly affected by the post-breakdown gate current.

SRAM reliability. The effect of gate-oxide breakdown on the stability of SRAM memory cells has been analysed. The worst cell stability has been obtained for gate oxide breakdown between gate and source of an n-FET of the cell. Breakdown leakage currents comparable to the fresh p-FET on-current produce a reduction of 50% of the static noise margin of the cell. The results are indicative of the gate-oxide breakdown leakage that can be allowed for a correct operation of the cells.

Effect of the dielectric degradation on CMOS inverter functionality. The effect of the n-FET and p-FET dielectric degradation on a CMOS inverter performance has been experimentally analysed and correctly simulated. The results show an increase/decrease of the higher/lower part of the inverter transfer curve, which also suffers a shift to the right/left hand side, when the n-FET/p-FET dielectric is degraded between gate and drain.

Impact of Negative Bias Temperature Instability (NBTI): The effect of NBTI at high frequency has been analysed, using specifically designed ‘on-chip circuits.. The threshold voltage change during dynamic tests (1Hz-2GHz) is one half of the measured under DC conditions. At circuit level, the maximum gain point in the transfer curve of a CMOS inverter is approximately one half of the variation observed in the PMOS threshold voltage of the inverter, independently of the stress frequency. This result demonstrates that NBTI impact on CMOS inverter is only due to the NBTI influence on the inverter PMOS transistor.

Time-dependent variability related to BTI effects in MOSFETs. A simulation methodology based on combined SPICE and Monte Carlo simulations has been proposed for the evaluation of the impact of process variations and oxide wear-out on the performance of devices and circuits. At device level, the methodology is able to reproduce the experimental observations only changing two of the physically meaningful parameters of the BSIM4 transistor model. At circuit level, the methodology has been used to evaluate the gain and bandwidth of differential amplifiers based in NMOS transistors taking into account the stress effects and the variability observed at device level.

Probabilitat de fallada d’amplificadors diferencials en funció del temps d’estrès i de la dispersió de la tensió llindar associada al procés de fabricació. La variabilitat del procés de fabricació pot tenir una gran influencia en la fiabilitat.

Cumulative failure distribution of differential amplifiers as a function of the stress time and the initial VT standard deviation associated to the fabrication process. The variability of the fabrication process can have an important influence in the reliability.

 

Electrical characterization and reliability of devices and circuits with high-k dielectric

 

Reliability of high-k based devices. MOS capacitors with dielectric stack of high-k and an interfacial layer of SiO2 have been subjected to static and dynamic tests. Positive static tests cause the larger degradation of the device, followed by the unipolar and bipolar ones. Under the same stress conditions, devices with a smaller SiO2 layer thickness (being the high-k layer equal) show larger degradation, which points out important impact of the interfacial layer on the degradation and BD of the gate stack.

Reliability of high-k based circuits. The influence of the metal gate on the reliability of a NMOS current mirror has been evaluated. The circuits fabricated with TiN gated devices are more robust to the electrical stress than those fabricated with poly-Si gated devices.

CHC degradation. A new proposal has been presented to explain the lifetime decrease observed  in the wide drain current range for short-channel transistors with high-k dielectric subjected to CHC stress.

Dielectric Breakdown reversibility. The resistive switching phenomenon is the conductivity change in the gate dielectric of Metal-Insulator-Metal (MIM) and Metal-Insulator-Semiconductor (MIS) structures. The resistive switching produces the change of the sample from a conductive state “ON state” to a lower conductive state “ OFF state” with the application of adequate voltages. We have observed that the resistive switching phenomenon can be produced in MIS devices with ultrathin (few nanometers) high-k dielectric based on Hafnium, totally compatible  with the CMOS process technology and it has been associated to the dielectric breakdown of the material when a current during the breakdown transient is limited.

 

Esquerra: Corbes IG-VG mesurades en un p-MOSFET després de successives iteracions de Current Limited- Ramp Voltage Stress (CL-RVS) i Ramp Voltage Stress (RVS). Un elevat corrent es registra després de la ruptura limitada en corrent (IBD) que cau sobtadame

Left: IG-VG curves measured in a p-MOSFET after successive Current Limited- Ramp Voltage Stress (CL-RVS) plus Ramp Voltage Stress (RVS) iterations. A high current is registered after the current limited BD (IBD) which suddenly drops after VR. During the CL-RVS in the next cycle , the gate current (IR) is larger than the fresh current (IF), but lower than IBD, which indicates a partial recovery of the dielectric properties.

Right: Top: A 5 stage ring oscillator was simulated to analyse the effects of dielectric BD and recovery on the circuit functionality. BD has been considered to be located at the drain of the third stage pMOS transistor. The pMOS electrical characteristics have been described using BSIM4 and D-R models (zoom).

Bottom: Circuit response when the third stage pMOS transistor is fresh (■), and working at BD (▲), or at R states (●).

 

Modelling of failure mechanisms for reliability analysis of complex systems

 

Piecewise model of the breakdown gate current of MOS devices. This is a circuit-design-oriented piecewise approximation that takes into account the statistical nature of the breakdown phenomenon and is able to consider the variability in current and breakdown times. The model allows to include the stress history and is easily extensible to different device geometries and operation conditions. The piecewise model has been applied to study the breakdown effect in current mirrors performance.

Equivalent circuit for the BTI recoverable component. The circuit, based on diodes and capacitors for easy incorporation in circuit simulators, is able to correctly reproduce the stress, relaxation, voltage, frequency and duty-cycle dependencies of the BTI-recovery component. The model allows the extrapolation of the BTI effects to very long stress times and has been used to evaluate the BTI effect in the delay time of CMOS inverters. 

 

 

SOME RELEVANT PUBLICATIONS

 

  • A. Crespo-Yepes, J. Martin-Martinez, A. Rothschild*, R. Rodriguez, M. Nafria and X. Aymerich, “Recovery of the MOSFET and circuit functionality after the Dielectric Breakdown of Ultra-Thin High-k Gate Stacks.", IEEE Electron Device Letters, Vol. 31 (6), pp. 543-545, 2010.
  • E. Amat, R. Rodríguez, M Nafría, X. Aymerich, T. Kauerauf, R. Degraeve and G. Groeseneken, “New insights into the wide ID range Channel Hot-Carrier degradation in high-k based devices”, International Reliability Physics Symposium (IRPS), pp. 1028-1032, 2009.
  • J. Martín-Martínez, R. Rodríguez, M. Nafría and X. Aymerich, “Time-Dependent Variability Related to BTI effects in MOSFETs: Impact on CMOS Differential Amplifiers”, IEEE Transactions on Device and Materials Reliability, Vol. 9, pp. 305-310, 2009.
  • R. Fernández, J. Martín-Martínez, R. Rodríguez, M. Nafría and X. Aymerich, “Gate oxide wear-out and breakdown effects on the performance of analog and digital circuits”, IEEE Transactions on Electron Devices, Vol. 55, pp. 997-1004, 2008.
  • J. Martín-Martínez, R.Rodríguez, M. Nafría, X. Aymerich, B. Kaczer and G. Groeseneken, “An equivalent circuit model for the recovery component of BTI”, Proc. European Solid State Devices and Research Conference, pp. 55-58, 2008.
  • R. Fernández, R. Rodríguez, M. Nafría, X. Aymerich, “Effect of oxide breakdown on RS latches”, Microelectronics Reliability, Vol. 47, pp. 581-584 (2007)
  • J. Martín-Martínez, R.Rodríguez, M.Nafría, X.Aymerich, J.H.Stathis, “Worn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirror”, Microelectronics Reliability, Vol. 47, pp. 665-668, 2007.
  • E. Amat, R. Rodríguez, M. Nafría, X. Aymerich, J.H. Stathis, “Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions”, Microelectronics Reliability, Vol 47, pp. 544-547, 2007.
  • R. Fernández, R. Rodríguez, M.Nafría y X. Aymerich, “MOSFET Output Characteristics After Oxide Breakdown”, Microelectronics Engineering, Vol. 84 (1), pp 31-36, 2007.
  • R. Fernández, B. Kaczer, A. Nackaerts, S. Demuynck, R. Rodríguez, M. Nafría and G. Groeseneken, “AC NBTI studied in the 1 Hz – 2 GHz range on dedicated on-chip CMOS circuits”, IEEE Int. Electron Device Meeting (IEDM) Tech. Digest, pp. 337-340, 2006.
  • R. Fernández, R. Rodríguez, M. Nafría and X. Aymerich, “Influence of oxide breakdown position and device aspect ratio on MOSFET’s output characteristics”, Microelectronics Reliability, Vol. 45(5-6), pp. 861-864, 2005.
  • R. Fernández, R. Rodríguez, M. Nafría and X. Aymerich, “A new approach to the modelling of oxide breakdown on CMOS circuits”, Microelectronics Reliability, Vol. 44, pp. 1519-1522, 2004.
  • R. Rodríguez, J. H. Stathis, B. P. Linder, “A model for gate oxide breakdown in CMOS inverters, IEEE Electron Device Letters, Vol. 24 (2), pp. 114-116, 2003.
  • R. Rodríguez, J. H. Stathis, B. P. Linder, S. Kowalczyk, C.T. Chuang, R.V. Joshi, G.Northrop, K. Bernstein, A. J. Bhavnagarwala, S. Lombardo, “The impact of gate oxide breakdown on SRAM stability”, IEEE Electron Device Letters, Vol. 23 (9), pp. 559-561, 2002.
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