Nanoscale characterization of the electrical properties and reliability of electron devices

As the dimensions of MOS devices are reduced, the local variations of their electrical properties become increasingly important to the global behaviour of the device, variations to which standard characterization techniques are blind. Therefore, techniques able to carry out a nanometer scale characterization are required as, for example, Scanning Probe Microscopy (SPM) techniques. Among them, Atomic Force Microscopy (AFM) related techniques are increasingly used for the study of nanoelectronic devices.

 

REDEC has applied Conductive Atomic Force Microscopy (CAFM) and other AFM related techniques to the study of the electrical properties of memories based on Si nanocrystals embedded in a SiO2 matrix and of the reliability of ultrathin SiO2 films subjected to electrical stresses or to irradiation/implantation processes, at nanometer scale. More recently, the use of these techniques has been extended to high-k dielectrics based devices, to study their reliability and the impact of different technological alternatives on their nanoscale electrical properties.

 

 

SOME RESULTS


CAFM set-up and measurements improvements

ECAFM and log-CAFM development. Two new prototypes of CAFM that overcome the limitations of standard configurations when applied for reliability studies have been developed: the ECAFM (Enhanced CAFM), and the log-CAFM. Both techniques have been applied to the study of SiO2 and high-k based devices reliability.

 

Corbes I-V mesurades amb l’ECAFM en el mateix punt d’un stack basat en una bicapa de HfO2/SiO2. La segona corba, en taronja, indica la ruptura de l’stack.

I-V curves mesured with ECAFM at the same HfO2/SiO2 stack point. The second curve, in orange, shows the breakdown point.

 

CAFM measurements in controlled ambient. CAFM measurements of gate dielectrics in controlled ambient (N2 or vaccum) have been demonstrated to be more reproducible.

 

SiO2 based devices

The SiO2 breakdown event at the nanoscale. The impact of a current limit on the post-BD oxide conductivity, the structural damage and the size of the breakdown spot has been evaluated. When a current limit is imposed during the stress, the breakdown event is less severe. However, the non-affected oxide region remains in a metastable situation that finally leads to a hard-breakdown event when the stress conditions are changed.

Irradiated SiO2 gate oxide. Different Atomic Force Microscopy related techniques (AFM) were used to analyze the electrical properties of ultra-thin gate oxides irradiated with heavy ions, gathering information on the size, position, electrical damage and number of conductive spots generated by the impinging particles. Only ~1-2% of the impinging ions produce a conductive path, associated to a SBD event. However, a higher percentage of ions may weaken the gate oxide (associated to the RILC observed at device level), resulting in the creation of conductive paths following subsequent electrical stresses.

Electrical characterization of implanted SiO2 layers. CAFM, SCM and KPFM have been used to qualitatively study and compare the impact of implantation and irradiation on SiO2 layers at different energies. The results show that C-AFM is able to detect differences in the case of implanted ions at different energies (3 and 30keV). The higher the energy, the larger the number of leaky sites. However, only ions with very high energy (irradiation) can induce BD events.

Si-nc based memories. C-AFM has been shown to be a very powerful tool to investigate at the nanoscale MOS structures with Silicon nanocrystals as memory devices. Our results demonstrate that Si-nc enhance the gate oxide electrical conduction due to trap-assisted tunneling through the Si-nc.. The amount of charge trapped in the nanocrystals and their retention time have also been determined. The observed electrical behavior at the nanoscale is consistent with the macroscopic characterization.

 

Imatge de corrent d’un spot de ruptura prèviament trencat amb la punta del CAFM en una capa de SiO2.

Current breakdown spot image broken with a CAFM needle in a SiO2 layer.

 

High-k based devices

Annealing and composition effects on the electrical characteristics of high-k dielectrics.

The dependence of the electrical conduction and the homogeneity of Hf based higk-k dielectrics on the Si diffusion and crystallization (which depend of the annealing temperature) has been analyzed. The impact of the different Hf compositions has also investigated. An increase of the annealing temperature and of the Hf concentration in the layer lead to smaller stack conductivity.

Reliability of high-k dielectrics. At low fields, the electrical stress provokes the trapping/detrapping of charges in HfO2 layer traps (as-grown and/or generated), whereas larger fields induce the degradation of the high-k and SiO2 layers. If the electrical field is large enough, the BD of the stack is induced, which is controlled by the SiO2 layer.

 

SOME RELEVANT PUBLICATIONS

 

  • M. Lanza, M. Porti, M. Nafría, X. Aymerich, E. Wittaker and B. Hamilton,"Electrical resolution during Conductive AFM measurements under different environmental conditions and contact forces", Review of Scientific Instruments, accepted for the publication on July 2010.
  • M.Lanza, M.Port, M.Nafria, X.Aymerich,G.Benstetter, E.Lodermeier, H.Ranzinger, G.Jaschke, S.Teichert, L.Wilde and P.Michalowski, "Conductivity and charge trapping after electrical stress in amorphous and polycristaline Al2O3 based devices studied with AFM related techniques", IEEE Trans. on Nanotechnology, accepted for the publication.
  • M. Porti, M. Avidano, M. Nafría, X. Aymerich, J. Carreras, O. Jambois, B. Garrido, “Nanoscale electrical characterization of Si-nc based memory MOS devices”, Journal of Applied Physics, 101, art. 064509, 2007.
  • L. Aguilera, M. Porti, M. Nafría y X. Aymerich, "Charge trapping and degradation of HfO2/SiO2 MOS gate stacks observed with Enhanced CAFM", IEEE Electron Device Letters, Vol. 27, No. 3, pp. 157-159, 2006.
  • M. Porti, M. Nafría, X. Aymerich, A. Cester, A. Paccagnella y S. Cimino, "Electrical characterization at a nanometer scale of weak spots in irradiated SiO2 gate oxides", IEEE Transactions on Nuclear Science, Vol. 52 (5), Part 2, pp. 1457–1461, 2005.
  • X. Blasco, M. Nafría, X. Aymerich, J. Pétry y W. Vandervorst, "Nanoscale post-breakdown conduction of HfO2/SiO2 MOS gate stacks studied by Enhanced-CAFM", IEEE Transactions on Electron Devices, Vol.52 (12), pp. 2817-2819, 2005.
  • X. Blasco, M. Nafría and X. Aymerich, "Enhanced electrical performance for conductive atomic force microscopy", Review of Scientific Instruments, Vol. 76 (1), No. 016105, 2005.
  • X. Blasco, J.Pétry, M. Nafría, X. Aymerich, O. Richard and W. Vandervorst, “C-AFM Characterization of the Dependence of HfAlOx Electrical Behavior on Post Deposition Annealing Temperature”, Microelectronic Engineering, Vol. 72 (1-4), pp.191-196, 2004.
  • M. Porti, M. Nafría and X. Aymerich, “Current limited stresses of SiO2 gate oxides with Conductive Atomic Force Microscope”, IEEE Transactions on Electron Devices, Vol. 50 (4), pp. 933-940, 2003.
  • M. Porti, M. Nafría, X. Aymerich, A. Olbrich and B. Ebersberger, “Nanometer-scale electrical characterization of stressed ultrathin SiO2 films using Conducting Atomic Force Microscopy”, Applied Physics Letters, Vol. 78 (26), pp. 4181-4183, 2001.
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